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'Knowledge is power' |
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I am pursuing my M.S. in electrical and electronics engineering at California State University, Sacramento after completing my B.E in electronics and communication engineering from Sardar Vallabhbhai Patel Institute of Technology which is affiliated to Gujarat University, India in the year 2007. I am specializing in microelectronics design which primarily includes analog and mixed signal IC design, VLSI testing, digital logic design and computer architecture. I am currently working on my master's project which CMOS PLL design in 0.5um process technology which is going to be taped out in summer 09. Also, I am working for my faculty advisor Dr. Perry Heedley as his teaching associate for EEE 230 (Analog and mixed signal IC design) and CSUS - IRT (Information, resources and technology) as the Classroom and lab assistant (CLA) in the CCLS departement. All of projects, achievements, resume attachments can be found on this webpage.... Please provide me your feedback with suggestions to improve my webpage at jaydip.patel@gmail.com
The webpage is still under construction..... |
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Updated on 01/23/2009 |
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