| Week 1: | Introduction, Gate Level Desig | | Full Adder | | ( Intro 2 ) | ||
| Week 2: | Gate Level - 2 | | Behavioral: (dff, counter) | | Verilog Design: (mux, muxb, rca4, csa4) | ||
| Week 3: | Behavioral 2: ( shiftreg, clkdiv ) | | FSM, Queues: (Part 1) | | FSM, Queues: (Part 2, repeat) | ||
| Week 4: | Functions & Tasks | | System Functions and Tasks | | Vending Machine | ||
| Week 5: | VHDL Construct | | Concurrency & Synthesis | | Midterm Review | ||
| Week 6: | Error Detection & Correction | | LFSR & CRC | | Midterm 1, Friday, 10/8/2021 | ||
| Week 7: | Resource Sharing & Other General Circuits | | General Circuits: Barrel Shifter, Gray Code, | Overflow, Arrary Mulitplier, Hamming Distance | ||
| Week 8. | Hazards, | ||||