Week 1: Introduction, Gate Level Desig | ( 2 ) | ( W1 - Exercise )
Week 2: Gate Level - 2 | Behavioral | Verilog Design | Sep.7, Labor Day Holiday
Week 3: Behavioral (2} | FSM, Queues (Part 1) | (Part 2) | ( W3 - Exercise )
Week 4: Functions & Tasks | System Functions and Tasks | ( W4 - Exercise)
Week 5: VHDL Construct | Currency & Synthesis | Synthesis (2), Hazards | ( W5 - Exercise)
Week 6: Error Detection & Correction | LFSR & CRC | ( W6 - Exercise1) | ( Exercise 2) | ( Exercise 3)
Week 7: Resource Sharing & Other General Circuits (2) | Midterm Review
Week 8: Timer,Pulse Generation & FIFO
Week 9: FSM | ASM | (2) | Metastability
Week 10: CAM, Pipeline | ASMD | ASMD (2) | ( W10 - Exercise_1)
Week 11: SRAM Handout (1), | decoder | SRAM (2) | SRAM (3) | ( W11 - Exercise_1) | Nov.11, Veteran's Day Holiday
Week 12: VGA | ( 1 ) | ( 2 ) | ( 3 ) | ( 4 )
Week 13: FPGA CPLD & FPGA Architecture | Nov. 26 - 27 Thanksgiving
Week 14: JTAG Boundary Scan (P1) | ( P2 ) | EXTEST
Week 15: Transmission Line | (2) | Clock Termination Techniques | Final Exam Review | Exercise
Week 16:
Final Exam Schedule: Wednesday 12/16/2020, 8 am - 10 am
Join the Zoom Meeting during the exam by using the regular Canvas CPE166 class zoom session.
