library ieee;
use ieee.std_logic_1164.all;
entity cir is
port(
     reset,clk, load: in std_logic;
     din :     in std_logic_vector(3 downto 0);
     dout :    out std_logic_vector(3 downto 0)
);
end cir;

architecture beh of cir is

begin
process (clk, reset, load)
begin
if (reset = '1') then
   dout <= "0000";
elsif (rising_edge(clk)) then
   if(load = '1') then
       dout <= din;
   end if;
end if;
end process;

	 
end beh;