library ieee;
use ieee.std_logic_1164.all;
entity cir2 is
port(
     din: in std_logic_vector(4 downto 1);
     dout :    out std_logic_vector(7 downto 1)    
);
end cir2;

architecture dataflow of cir2 is
signal p4, p2, p1: std_logic;
begin

   -- din(4): bit 7,  din(3): bit 6, din(2): bit 5;  p4: bit 4; din(1): bit 3. p2: bit 2; p1: bit 1.

   p4 <= din(4) xor din(3) xor din(2);   
   p2 <= ... ;
   p1 <= ... ;

   dout <= din(4) & din(3) ..... ;   

	 
end dataflow;