IBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cir3 is
 port(clk1 : in std_logic;
 clk2 : out std_logic);
end cir3;

architecture beh3 of cir3 is
signal counter: std_logic_vector(7 downto 0);
begin
s
 process (clk1)
 begin
 if (rising_edge(clk1)) then
   if (counter=249) then
     clk2 <= '1';
     counter <= (others=>’0’);
   elsif(counter<124) then
     clk2 <= '1';
     counter <= counter + 1;
   else
     clk2 <= '0';
     counter <= counter + 1;
   end if;
 end if;
 end process;

end beh3;