library ieee;
use ieee.std_logic_1164.all;
entity fsm_exe2 is
port(
     reset,clk: in std_logic;
     a :    in std_logic;
     y :       out std_logic
);
end fsm_exe2;

architecture arch2 of fsm_exe2 is

type state_type is (S0, S1, S2, S3 );

signal cs, ns: state_type;

begin
process (clk, reset)
begin
if reset = '1' then
   cs <= S0;
elsif (rising_edge(clk)) then
   cs <= ns;
end if;
end process;

process(cs, a)
begin
case cs is
when S0=> if (a = '1') then
             ns <= S1;
          else
             ns <= S0;
          end if;
when S1=> if (a = '1') then
             ns <= S2;
          else
             ns <= S1;
          end if;
when S2=> if (a = '1') then
             ns <= S3;
          else
             ns <= S1;
          end if;
when S3=> if (a = '1') then
             ns <= S0;
          else
             ns <= S1;
          end if;
when others=> ns <= S0;
end case;
end process;

y <= '1' when (cs=S3) and (a='0') else 
     '0';
	 
end arch2;