library ieee;
use ieee.std_logic_1164.all;
entity fsm_exe3 is
port(
     reset,clk: in std_logic;
     a :    in std_logic;
     y :       out std_logic
);
end fsm_exe3;

architecture arch3 of fsm_exe3 is

type state_type is (S0, S1, S2, S3 );

signal cs: state_type;

begin

process (clk, reset)
begin
if (reset = '1') then
   cs <= S0;
elsif (rising_edge(clk)) then
    case cs is
      when S0=>  if (a = '1') then
                 cs <= S1;
                else
                 cs <= S0;
                end if;
      when S1=>  if (a = '1') then
                 cs <= S2;
                else
                 cs <= S1;
                end if;
      when S2=> if (a = '1') then
                 cs <= S3;
                else
                 cs <= S1;
                end if;
      when S3=> if (a = '1') then
                  cs <= S0;
                else
                  cs <= S1;
                end if;
      when others=> cs <= S0;
    end case;
end if;
end process;

y <= '1' when (cs=S3) and (a='0') else 
     '0';
	 
end arch3;