Syllabus   


Lab 2 Report Grading Sheet (Click)
Lab 3 Report Grading Sheet (Click)
Lab 4 Report Grading Sheet (Click)
Lab 5 Report Grading Sheet (Click)

For Monday CPE166 lab students, submit your lab reports to cpe20201@gmail.com, lab instructor: Dhwanit Arunkumar Juneja
For Tuesday CPE166 lab students, submit your lab reports to cpe2020tue@gmail.com lab instructor: Jonghee Sang
For Thursday CPE166 lab students, submit your lab reports to cpe20204@gmail.com lab instructor: Harpreet Sidhu



Quiz 1: Friday 2/7/2020 inside classroom.
Quiz 1: closed book, closed notes, no cheat-sheets.
The total score for Quiz 1 is 10.
Any student who fails to take the quiz on time will be penalized.
A delay of 1 week will result in a 1 point grade deduction.
Any delay of more than 2 weeks will not be accepted.

Urgent Annoucement
Message from President Nelson: " Monday, March 16, to Thursday, March 19, 2020 - All instruction (face-to-face, online, lab, studio, exams, and assignments) will be suspended to provide faculty time to prepare and transition their courses online. No classes (including classes currently online) will be held during this period. Field-based assignments, internships, and clinical placements will continue if the site is still hosting student placements. The campus will remain open.
Friday, March 20, to Wednesday, May 14, 2020 - All courses with the exception of approved in-person courses (e.g., small labs, studios, clinicals, field placements, and performing and theater arts) will be conducted online. There will be no in-person finals in any courses unless approved by the Dean and Provost."

There won't be any CPE166 class from Monday, March 16, to Thursday, March 19, 2020.
Starting from March 20, 2020 to May 14, 2020, all of in-class meeting will be replaced by online zoom virtual meeting from Canvas at our normal class time.
In another word, you need to log in to Canvas to attend the virtual class meeting at our normal class time starting from March 20, 2020.

Original policy of "Quiz 3% Labs 37% Midterm 1 20% Midterm 2 20% Final (Comprehensive) 20%" for your course grade will be updated to: 3% Credit, Labs 37%, Midterm 30%, Final (Comprehensive) 30% of your grade.
This means everybody gets 3% credit by default to replace the original 3% quiz grade. I won't give any more quizzes. You can practice by looking at exercise questions I posted on course website.
In addition, Lab3 Part 3 - Calculator Design project is canceled.
Every student just needs to complete Lab 3 - Part 1, Part 2 and Part 4 projects to get 100. As a result, now part 1 is 33 points, part 2 is 33 points, and part 4 is 34 points.
Any student who can complete the calculator design project by the report deadline for Lab 3 will receive 25 additional credits.

Important:
During normal lab hours, all students must stay at home instead of going to the lab to work on lab projects. During your normal lab hours, all lab instructors will provide guidance online.

******************* Lab 3 Project 2 demo deadline will be extended to week 11 (Apr. 6 - Apr. 10) during your normal lab time. ********


******************* All Labs should be conducted during normal lab time. ************************
Lab 3 Part 2 Due Time: Week 11, April 6 - April 10.
Lab 3 Part 4 Start Time: Week 12, April 13 - April 16.
Lab 3 Part 4 Due Time: Week 13, April 20 - April 23
Lab 3 Part 3 Extra Credit Due Time: Week 13, April 20 - April 23
Lab 3 Report Due: Week 14 Friday.

Lab 4: Start time: Week 13: April 20 - April 23
Lab 4: Due time: Week 15: May 4 - May 7
Lab 4 Report Due Time: Sunday of Week 15
Lab 5 will be cancelled.
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Lecture Notes:

Introduction    |   Ex_S0 (basic)   |   Gate Level in Verilog   |   Testbench in Verilog

Ex_S1 (adders)   |  Full Adder   |  Ex_S1.1(different mux)   |  Ex_RCA4(4-bit Ripple Carry Adder)   |  Carry Select Adder   |  Hiearchical Design(Gate Level)  

Ex_S2 (D Flip-Flops, Shift Registers, Adder)   |   Mult |   Ex_S3 (FSM)   |   Queues, FSM   |   Behavioral Design (c7)  

********************************************** * FPGA Pins * **********************************************

Multiplexed Character Display   |   FPGA Fun (Pins)   |   Behavioral Design (c7)   |   Verilog Behavioral Modelling (c8)  

********************************************************************************************************
* Week 5: Midterm 1 Review. Week 6: Miderm 1 *
Week 5: Feb. 17 ~ Feb. 21;      Week 6: Feb. 24 ~ Feb. 28
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Week 5: Midterm Review; |   VHDL Basics   |   Intro to VHDL   |   Counter (VHDL)  

Week 6: Midterm 1 (Friday, 10/4/2019); |   Intro to VHDL (Part 2)   |   LFSR  

Conditional Assignment   |   Hamming Code   |   ASM Charts   |   ASM Charts Diagrams   |   ( 2 )   |   FSM-VHDL  

Exercise: FSM, |   ( 1 ) |   ( 2 ) |   ( 3 ) |   ( cir ) |   ( cir2 ) |   ( cir3 )  
Exercise: Gray Counter   |   ASM Chart   |   ( cir4 ) |   DICE  

Parity (Verilog)   |   Parity (VHDL)   |   CRC   |   Display   |  

Week 9: SRAM Handout (1),   |   decoder   |   SRAM (2)   |   SRAM (3)   |   mem_fsm   |   mem_top   |   FIFO  

Week 10: Metastability,   |   (1)   |   (2)   |   Midterm 2 Review

********************************************************************************************************
* Week 10: Midterm 2 Review. Week 11: Miderm 2 *
Week 10: Mar. 23 ~ Mar. 27;      Week 11: Apr. 6 ~ Apr. 10
********************************************************************************************************

Week 11: Hazards,   |   Extra |   Exe2 |   Exe3 |   Midterm 2

Week 12: VGA   |   ( 1 )   |   ( 2 )   |   ( 3 )  

Week 13: CPLD & FPGA Architecture   |   ILA  

Week 14: JTAG Boundary Scan (P1)   |   ( P2 )   |   EXTEST  

Week 15: Transmission Line   |   Clock Termination Techniques