library ieee;
use     ieee.std_logic_1164.all;

entity dff_vh is 
   port(clk,clr, ce, d:  in std_logic; 
        q:  out std_logic);

end dff_vh;
architecture beh of dff_vh is
begin
    process(clk, clr, ce)
    begin
       if(clr='1') then
            q <= '0';
       elsif(rising_edge (clk)) then

          if(ce='1') then
            q <=  d;
          end if;
       end if;
    end process;
end beh;