# Pin assignment
set_property -dict { PACKAGE_PIN A4  IOSTANDARD LVCMOS33 } [get_ports { red[3] }];     # VGA_R3
set_property -dict { PACKAGE_PIN C5  IOSTANDARD LVCMOS33 } [get_ports { red[2] }];     # VGA_R2
set_property -dict { PACKAGE_PIN B4  IOSTANDARD LVCMOS33 } [get_ports { red[1] }];     # VGA_R1
set_property -dict { PACKAGE_PIN A3  IOSTANDARD LVCMOS33 } [get_ports { red[0] }];     # VGA_R0

set_property -dict { PACKAGE_PIN A6  IOSTANDARD LVCMOS33 } [get_ports { green[3] }];     # VGA_G3
set_property -dict { PACKAGE_PIN B6  IOSTANDARD LVCMOS33 } [get_ports { green[2] }];     # VGA_G2
set_property -dict { PACKAGE_PIN A5  IOSTANDARD LVCMOS33 } [get_ports { green[1] }];     # VGA_G1
set_property -dict { PACKAGE_PIN C6  IOSTANDARD LVCMOS33 } [get_ports { green[0] }];     # VGA_G0

set_property -dict { PACKAGE_PIN D8  IOSTANDARD LVCMOS33 } [get_ports { blue[3] }];     # VGA_B3
set_property -dict { PACKAGE_PIN D7  IOSTANDARD LVCMOS33 } [get_ports { blue[2] }];     # VGA_B2
set_property -dict { PACKAGE_PIN C7  IOSTANDARD LVCMOS33 } [get_ports { blue[1] }];     # VGA_B1
set_property -dict { PACKAGE_PIN B7  IOSTANDARD LVCMOS33 } [get_ports { blue[0] }];     # VGA_B0

set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { hsync }];         # VGA_HS
set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsync }];         # VGA_VS
set_property -dict { PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports { clk }];            # CLK100MHZ

# Clock definition
create_clock -name sys_clk -period 10.00 [get_ports {clk}];                          # 100 MHz
create_generated_clock -name pclk -source [get_ports {clk}] -divide_by 4 [get_pins {pxclk[1]/Q}];   # 25 Mhz

set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { clr }];

# Configuration Bank Voltage Select
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]