module cir(clk, clk2);
input  clk;
output clk2;
reg    clk2;
reg   [3:0] cnt;

always@(posedge clk)
begin
      if(cnt == 9)
      begin
        clk2 <= 1;
        cnt  <= 0;
      end
      else if (cnt < 4)
      begin
        clk2 <= 1;
        cnt  <= cnt + 1;
      end
      else
      begin
         clk2 <= 0;
         cnt  <= cnt + 1;
      end
end

endmodule