`timescale 1 ns / 100 ps
module cir(a, b, f);
 
 input  a, b;
 output f;
 
 assign f = a | b;
   
endmodule
 
`timescale 1 ns / 100 ps
module cir_tb;
 
 reg  a, b;
 wire f;
 
 cir g1 ( a, b, f);
 
 initial  begin
 
   a = 0; b = 0;
   #2 check_res( f, 0 );

   
   a = 0; b = 1;
   #2 check_res( f, 1 ); 

   a = 1; b = 0;
   #2 check_res( f, 1 ); 

   
   a = 1; b = 1;
   #2 check_res( f, 1 );
   
   #10 $stop;
   
 end  
 
 task check_res;
 input data;
 input res;
 begin
   if( data != res) $display($time, "ns, Error: a=%b, b=%b, Expected value = %d, Actual value = %d \n", a, b,  res, data);
 end
 endtask
 
 

 


endmodule