module myand(a,b,f);
input  a, b;
output f;
assign f = a & b;
endmodule

module myand_tb;
reg   a, b;
wire  f;
integer k;

myand uut(a, b, f);

initial
begin
  $monitor($time, " ns, a=%b, b=%b, f=%b", a, b,f);
  { a, b} = 2'b00;
  for (k=0; k<4; k=k+1)
    #5 {a, b} = k;
  #5 $stop;
end
endmodule