module fifo(clk, rst, wr, rd, full, empty, w_addr, r_addr);
input    clk, rst, wr, rd;
output   full, empty;
output [2:0]  w_addr, r_addr;
reg    [3:0]  w_ptr, r_ptr;

always@(posedge clk or posedge rst)
begin
   if(rst)
   begin
     w_ptr <= 0;
     r_ptr <= 0;
   end
   else
     if(wr && !full)
       w_ptr <= w_ptr + 1;
     if(rd && !empty)
       r_ptr <= r_ptr + 1;
end

assign full = ((r_ptr!=w_ptr) && (r_ptr[2:0]==w_ptr[2:0]))?1:0;
assign empty = (r_ptr==w_ptr) ? 1 : 0;

assign w_addr = w_ptr[2:0];
assign r_addr = r_ptr[2:0];

endmodule



module fifo_tb;
reg    clk, rst, wr, rd;
wire   full, empty;
wire  [2:0]  w_addr, r_addr;

fifo uut(clk, rst, wr, rd, full, empty, w_addr, r_addr);

always #10 clk=~clk;

initial 
begin
     $monitor($time, " ns,  wr=%b, rd=%b, w_addr=%d, r_addr=%d, full=%b, empty=%b", wr, rd, w_addr, r_addr, full, empty); 
     rst = 1; wr=1; rd = 0; clk=0;
     #5 rst=0;
     #60;
     wr=0; rd = 1;
     #40;
     wr = 1; rd = 0;
     repeat (10)  @(negedge clk);
     wr = 0; rd = 1;
     repeat (10)  @(negedge clk);
     #20 $stop;
end
endmodule