module ram (clk, w_addr, din, we, oe, r_addr, dout);
input clk;
input [2:0] w_addr;
input [15:0] din;
input we, oe;
input [2:0] r_addr;
output [15:0] dout;
reg [15:0] ram_reg;
reg [15:0] memory [7:0];
integer    i;

initial begin
  for (i = 0; i <= 7; i = i + 1) begin
       memory [i] = 16'h0000;
  end
  memory [0] = 16'h000a;
  memory [1] = 16'h0014;
  memory [2] = 16'h001e;
  memory [3] = 16'h0032;
  #1;
  for (i = 0; i <= 7; i = i + 1) begin
       $display(" Address = %d,  Memory Data = %h",i,memory [i]);
  end
end

always @(posedge clk)
begin

if (we)
memory[w_addr] <= din;
end

always @(posedge clk) begin
ram_reg <= memory[r_addr];
end

assign dout = (~we && oe) ? ram_reg : 16'hzzzz;

endmodule


//=================================================================

module ram_fsm (clk, reset, we, oe, w_addr,  r_addr);
input clk, reset;
output [2:0] w_addr;
output we, oe;
output [2:0] r_addr;

reg          we, oe;
reg    [2:0] r_addr, w_addr;
parameter  idle=3'b000, r0=3'b001, s_read=3'b010,  w0=3'b011, s_write=3'b100, s_halt=3'b101 ;
reg   [2:0] cs;
always@(posedge clk)
begin
   if(reset)  cs <= idle;
   else
     case(cs)
     idle: begin
            r_addr <= 0;
            w_addr <= 0;
            we <=0;
            oe <=0;
            cs <= w0;
           end
     w0:   begin
            r_addr <= 0;
            w_addr <= 0;
            we <= 1;
            oe <= 0;
            cs <= s_write;
           end
      s_write: begin
               r_addr<=0;
               w_addr <= w_addr + 1;
               we <= 1;
	       oe <= 0;
               if(w_addr < 7)               
                  cs <= s_write;
               else
		        cs <= r0;
            end
       r0:  begin
               w_addr<=0;
               r_addr <= 0;
               we <= 0;
	       oe <= 1;
                             
               cs <= s_read;            
		  
            end
       s_read:  begin
               w_addr<=0;
               r_addr <= r_addr + 1;
               we <= 0;
	       oe <= 1;
               if(r_addr < 7)               
                  cs <= s_read;
               else
		  cs <= s_halt;
            end

       s_halt:  begin
               w_addr<=0;
               r_addr <= 0;
               we <= 0;
	       oe <= 0;           
               cs <= s_halt;
            end
       endcase
  end
endmodule

module top(clk, reset, din, dout);
input  clk, reset;
input  [15:0] din;
output [15:0] dout;

wire [2:0] w_addr, r_addr;
wire       we, oe;

ram     g1(clk, w_addr, din, we, oe, r_addr, dout);
ram_fsm g2(clk, reset, we, oe, w_addr,  r_addr);

endmodule