`timescale 1ns/1ns
module tb;
reg  reset, clk;
reg  [15:0] din;
wire [15:0] dout;

mydesign uut (reset, clk, din, dout);

always #10  clk=~clk;

initial begin
   clk = 0;
   reset = 1;
   #10 reset = 0;
   repeat (8)
   begin
     @(negedge clk);
     din = 16'h6688;
   end
   #2 din=16'h0000;
   repeat(8)
     @(negedge clk);
  #20 $stop;     
end

initial $monitor($time, " ns, clk=%b, din=%h, dout=%h", clk, din, dout);

endmodule
     



module mydesign(reset, clk,  din,  dout);
input         reset, clk;
input  [15:0] din;
output [15:0] dout;

reg           we, oe;
reg  [2:0]    w_addr;
reg  [2:0]    r_addr;

reg    [2:0]  state;
parameter  idle=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;

ram  g1(clk, w_addr, din, we, oe, r_addr, dout);

always@(posedge reset or posedge clk)
begin
   if(reset)  state <= idle;
   else
     case(state)
       idle:   begin w_addr <=0;  r_addr <= 0;  state <= s1; end
       s1:     begin w_addr <=0;  r_addr <= 0;  state <= s2; end
       s2:     begin 
                 w_addr <= w_addr + 1; r_addr <= 0;
                 if (w_addr < 7)
                      state <= s2;
                 else
                      state <= s3;
               end
       s3:     begin w_addr <=0;  r_addr <= 0;  state <= s4; end
       s4:     begin
                  r_addr <= r_addr + 1; w_addr <= 0;
                  if (r_addr < 7)
                      state <= s4;
                 else
                      state <= s5;
       
               end
       s5:     begin w_addr <=0;  r_addr <= 0;  state <= s5; end
       default: begin w_addr <=0;  r_addr <= 0;  state <= idle; end
     endcase
end

always@(state)
     case(state)
       idle:   begin we <=0;  oe <= 0;   end
       s1:     begin we <=1;  oe <= 0;   end
       s2:     begin we <=1;  oe <= 0;   end
       s3:     begin we <=0;  oe <= 1;   end
       s4:     begin we <=0;  oe <= 1;   end
       s5:     begin we <=0;  oe <= 0;   end
       default: begin we <=0;  oe <= 0;  end
     endcase
    
endmodule


module ram (clk, w_addr, din, we, oe, r_addr, dout);
input clk;
input [2:0] w_addr;
input [15:0] din;
input we, oe;
input [2:0] r_addr;
output [15:0] dout;
reg [15:0] ram_reg;
reg [15:0] memory [7:0];
integer    i;

initial begin
  for (i = 0; i <= 7; i = i + 1) begin
       memory [i] = 16'h0000;
  end
  memory [0] = 16'h000a;
  memory [1] = 16'h0014;
  memory [2] = 16'h001e;
  memory [3] = 16'h0032;
  #1;
  for (i = 0; i <= 7; i = i + 1) begin
       $display(" Address = %d,  Memory Data = %h",i,memory [i]);
  end
end

always @(posedge clk)
begin

if (we)
memory[w_addr] <= din;
end

always @(posedge clk) begin
ram_reg <= memory[r_addr];
end

assign dout = (~we && oe) ? ram_reg : 16'hzzzz;

endmodule