| Week 1: |
Introduction, Gate Level Desig |
| Full Adder |
| ( Intro 2 ) |
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| Week 2: |
Gate Level - 2 |
| Behavioral: (dff, counter) |
| Verilog Design: (mux, muxb, rca4, csa4) |
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| Week 3: |
Behavioral 2: ( shiftreg, clkdiv ) |
| FSM, Queues: (Part 1) |
| FSM, Queues: (Part 2, repeat) |
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| Week 4: |
Functions & Tasks |
| System Functions and Tasks |
| Vending Machine |
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| Week 5: |
VHDL Construct |
| Concurrency & Synthesis |
| Midterm 1 Review |
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| Week 6: |
Error Detection & Correction |
| LFSR & CRC |
| .. |
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| Week 7: |
Resource Sharing & Other General Circuits |
| General Circuits: Barrel Shifter, Gray Code, |
Overflow, Arrary Mulitplier, Hamming Distance |
Midterm 1, Friday, 3/11/2022 |
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| Week 8. |
General Circuits: |
| Hazards |
| Timer, Pulse Generation & FIFO |
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| Week 9. |
FSM |
| ASM, ( Part 2 ) |
| Metastability |
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| Week 10. |
Memory |
| Memory, SRAM (2) , ( 3 ) |
| Midterm 2 Review |
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| Week 11. |
Midterm 2 Review |
| CAM |
| Midterm 2, Friday, 4/15/2022 |
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| Week 12 |
Pipeline |
| VGA | ( 1 ) | ( 2 ) | |
| VGA ( 3 ) ( 4 ) |
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| Week 13 |
CPLD & FPGA Architecture |
| CPLD & FPGA Architecture |
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| Week 14 |
JTAG Boundary Scan (P1) |
| JTAG (P2) |
| EXTEST |
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| Week 15 |
Transmisssion Line, |
| ( 2 ) |
| Final Exam Reveiw |
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| Week 16 |
Final Exam |
Final Exam
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