| Week 1: | Introduction, Gate Level Desig | | ( 2 ) | |||
| Week 2: | Gate Level - 2 | | Behavioral | | Verilog Design | ||
| Week 3: | Behavioral (2} | | FSM, Queues (Part 1) | | (Part 2) | ||
| Week 4: | Beverage Vending Machine | | Function and Tasks | | System Functions & Tasks | ||
| Week 5: | VHDL Construct | | Currency & Synthesis | | Synthesis (2), Hazards | ||
| Week 6: | Error Detection & Correction | | LFSR | | CRC | ||
| Week 7: | Resource Sharing & Other General Circuits, | | Midterm Review | | Midterm Review | ||
| Note: | April 5th, 2021, | Midterm on Monday | |||
| Week 8: | Timer, Pulse Generation | | Review | | FSM | ||
| Week 9: | Algorithmic State Machine Chart | | ASM (2) | | Metastability | ||
| Week 10: | 4/5/2021 Mon. Midterm, | | CAM | | Midterm Paper Review | ||
| Week 11: | Pipeline | | ASMD | | ASMD ( 2 ), SRAM | ||
| Week 12: | SRAM ( 2 ) ( 3 ) | | sim-Mic, VGA ( 1 ) ( 3 ) | | VGA ( 2 ) ( 4 ) | ||
| Week 13: | VGA ( 2 ) ( 4 ) | | CPLD | | FPGA | ||
| Week 14: | JTAG Boundary Scan P1 | | ( Part 2 ) | | EXTEST | ||
| Week 15: | Transmission Line | | ( Part 2 ) | | Final Review | ||
| Week 16; | Final Exam Schedule: | Wed., May 19 7:30am - 10:00am |
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