Professor Pang's CPE166 Class
Welcome to Professor Pang's CPE166 Class
Syllabus
Lecture Notes:
My class lecture notes are part of my intellectual property and they are based on my hard work!
Please don't submit them to external websites without my permission! - By Prof. Pang
Week 1:
Introduction, Gate Level Design
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Full Adder
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( Intro 2 )
Week 2:
Gate Level - 2
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Behavioral: (dff, counter)
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Verilog Design: (mux, muxb, rca4, csa4)
