| w1. |
Number System |
| Number Conversion |
| Number Conversion ( Part 2 ) |
| Logic Gates |
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| w2. |
w1, w2: Classes online |
| Combinational Logic Gates |
| Boolean Algebra ( Part 1 ) |
| Logic Gates ( Part 2 ) |
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Boolean Algebra ( Part 2 ) |
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| w3. |
Boolean Algebra ( Part 3 ) |
| Boolean Algebra ( Part 4 ) |
| K-Map ( SOP ) |
| K-Map ( SOP - Part 2) |
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| w4. |
DeMorgan's Law |
| Boolean Algebra Summary |
| K-Map ( POS ) |
| Comparator |
| Verilog |
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| w5. |
Decoder, Encoder |
| Exercise ( 1 ), ( 2 ), ( 3 ) |
| Multiplexer, Demultiplexer |
| Verilog |
| Exercise ( 4 ),( 5 ) |
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| w6. |
Priority Encoder, Verilog |
| Decoder ( 2 ) |
| Seven Segment Display |
| Half Adder, Full Adder |
| Signed Arithmetic |
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| w7. |
2's Complement Adder/Subtractor |
| Overflow |
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| Midterm Review |
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| w8. |
NAND, NOR SR Latches |
| Exercise ( 1 ) |
| Clocked SR Latch |
| SR Master-Slave Flip-Flop |
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Clocked SR Ltch, D Latch |
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Edge-Triggered D Flip-flop |
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| w9. |
Exercise w8 ( 2 ) |
| Exercise w8 ( 3 ) |
Wednesday:
4/6/2022
Midterm |
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| w10. |
Sequential (1): T Flip-Flop, (2: Intro) |
| Sequential (3): Registers |
| Sequential ( 4 ): Counters |
| Midterm Exam Paper Review |
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| w11. |
Verilog, Seq. Analysis & Design (1) |
| Seq. Analysis & Design (2) |
| Seq. Analysis & Design (3) |
| Intro. to FSM, ( 2 ), Verilog |
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| w12. |
Exercise ( 1 ) ( 2 ) |
| Exercise ( 3 ) ( 4 ) |
| Prog. Imp. Tech. & Mem. Basics |
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| w13. |
Prog. Imp. Tech. & Mem. Basics |
| Computer Basics |
| Computer Basics ( 2 ) |
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| w14. |
Computer Basics (2) |
| Exercise 14. 1 |
| Exercise 14.2 |
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| w15. |
Final Exam Review |
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| Final Exam Review |
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| w16. |
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Final Exam
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