w1. Number System | ( Set 1 )
w2. Logic Gates, Boolean Algebra, Truth Tables, Logic Design | ( Set 2 ) | ( Set 2.2 )
w3.4. Logic Gates, Boolean Reduction, Minterms, Maxterms, KarnaughMap | ( Set 3 ) | ( Set 3.2 ) | ( Set 4 )
w5. Multiplexers, Demultiplexers, Encoders and Decoders | Seven Segment Display | ( Set 5 )
w6. Signed Number, Adder, Subtractor | Comparator | ( Set 6 )
w7. Midterm Review |
w8. SR Latches, D Latches & D Flip-Flops | ( Set 7 )
w9. Sequential Circuit Analysis and Design | ( Set 8 ) | Midterm
w10. Registers, Counters | ( Set 9 ) | ( Set 10 ) | ( Set 11 ) | ( Set 12 )
w11. Introduction to State Machine | Nov. 11 Veteran's Day | ( w11 set )
w12. Verilog & More | ( w12 set )
w13. Programmable Implementation Technologies & Memory Basics | ( Nov. 26 - 27 Thanksgiving )
w14. Computer Design Basics, ALU and Shifter, Tri-State Device
w15. Final Review | ( === Final Set Exercise ===)