Welcome to Professor Pang's EEE/CPE64 Class

Number System

| 

 Number Conversion

|  ( 2 )

| 

w2.  

Logic Gates

|   Part 2        |  Logic Algebra

|  DeMorgan's Laws

| 

w3.

Karnaugh Map (K-Map)

|   SOP, Minterm          

|   POS, Maxterm

| 

w4.

Consensus Law

|  2-Bit Greater Than Comparator

|   Verilog Design 

| 

w5.  

Combinational Circuit

|  Verilog      |  Decoder, Encoder

|  Verilog (5.2) |  Mux

| 

w6.

Mux vs. Demux

|  Seven Segment Display

|  Half Adder,  Full Adder

w7. 

Signed Number

| Signed Addition,   Midterm Review

|  Midterm Review

w8.

Signed Subtraction

|  Adder / Subtractor

w8.

NAND SR Latch
NOR    SR Latch

|  D Latch, D Flip-Flops

Midterm Update:

w9.

Programmable Implementation Technologies & Memory Basics 

w10.

Midterm Review

Wednesday, Midterm

w11.

Sequential,   (2)

Sequential (3) ,
Midterm Paper Review

w12.

Sequential (4),  ( 5 )

|  Intro to FSM

|  Intro to FSM (2)

|

w13.

Intro to FSM

| (set w11.2),  (set w11.3)

|  Memory Basics

| 

w14.

Computer Basics

|  Computer Basics ( 2 )

| 

w15.

Final Review

|  Final Review

w16.

Final Exam: 

Time