Professor Pang's EEE/CPE64 Class

Welcome to Professor Pang's EEE/CPE64 Class

Lecture Notes:

w1.	Number System	\| Introduction to Logic Design	\| Number Conversion	\| ( 2 )	\| ( set1 )

w2.	Logic Gates	\| Part 2 \| Logic Algebra	\| DeMorgan's Laws	\| ( set 2.1 )	\| ( set 2.2 )
				\| ( set2.3 )	\| ( set2.4 )

w3.	Karnaugh Map (K-Map)	\| SOP, Minterm	\| POS, Maxterm	\| (set 3 )	\| ( set 3.2 )	\| ( set 4 )

w4.	Consensus Law	\| 2-Bit Greater Than Comparator	\| Verilog Design	\| ( set 3.c )	\| ( set3.v )

w5.	Combinational Circuit	\| Verilog \| Decoder, Encoder	\| Verilog (5.2) \| Mux	\| ( set w5.1)	\| (set w5.2)	\| ( set w5.3 )
				\| (set w5.4 )	\| (set w5.5)

w6.	Mux vs. Demux	\| Seven Segment Display	\| Half Adder, Full Adder

w7.	Signed Number	\| Signed ddition, Midterm Review	\| Midterm Review

w8.	Signed Subtraction	\| Adder / Subtractor

w8.	NAND SR Latch NOR SR Latch	\| D Latch, D Flip-Flops