Course Final Exam Annoucement:
CPE166 Final Exam Schedule inside your classromm:
CPE166: 12/11/2019, Wednesday 8 am - 10:00 am
Course Annoucements:
1. Because 9/2/2019 (Monday) is holiday, Lab2 part 1 demo for Monday lab students will be extended to Week 5 Monday lab session.
All other labs of lab 2 will still follow the schedule posted on the syllabus.
Lab2 Report submission deadline will also follow the schedule posted in the syllabus.
2. Quiz 1: Friday 9/13/2019 inside classroom.
Quiz 1: close book, close notes and no cheat-sheets.
Quiz 1: you need to review half adder design and testbench, mux2to1 design and testbench,
any general combinational circuit design when schemtic is given and testbench,
basic rising edge triggered D Flip-flop design and testbench before you attend the quiz.
All of students must take the quiz1 on Friday 9/13/2019.
No make-up quiz will be given if you miss the quiz.
Your quiz 1 grade will be zero if you miss the quiz inside the classroom on Friday, 9/13/2019.
3. *** Important Announcement ****
Week 6: Midterm 1 (Friday, 10/4/2019)
4. *** Extention of Lab 2 Part 2 Demo Deadline
Lab 2 part 2 demo deadline is extended to week 6 (9/30/2019 ~ 10/4/2019).
Show your demo during your lab session.
All other project deadlines remain the same as posted in the syllabus.
5.
*** All of lab reports are due on Friday as shown in the syllabus.
For Tuesday and Thursday CPE166 lab students,
submit your lab report to cpe166labs1@gmail.com
Your lab instructor is Yaseen,Sarmad K and his contact email is : s.khalooq@yahoo.com
For Monday CPE166 lab students,
submit your lab report to cpe166labs2@gmail.com
Your lab instructor is Sidhu,Harpreet S and his contact email is: happy73093@gmail.com
6.
Quiz 2: Friday 10/25/2019 inside classroom.
Quiz 2: close book, close notes and no cheat-sheets.
Quiz 2: VHDL only.
No make-up quiz will be given if you miss the quiz.
Your quiz 2 grade will be zero if you miss the quiz inside the classroom on Friday, 10/25/2019.
Introduction | Ex_S0 (basic) | Gate Level in Verilog | Testbench in Verilog
Ex_S1 (adders) | Full Adder | Ex_S1.1(different mux) | Ex_RCA4(4-bit Ripple Carry Adder) | Carry Select Adder | Hiearchical Design(Gate Level)
Ex_S2 (D Flip-Flops, Shift Registers, Adder) | Mult | Ex_S3 (FSM) | Queues, FSM | Behavioral Design (c7)
********************************************** * FPGA Pins * **********************************************
Multiplexed Character Display | FPGA Fun (Pins) | Behavioral Design (c7) | Verilog Behavioral Modelling (c8)
******************************************************************************************************** * Week 5: Midterm 1 Review. Week 6: Miderm 1 * Week 5: Sep. 23~27; Week 6: Sep. 30 ~ Oct. 4 ********************************************************************************************************
Week 5: Midterm Review; | VHDL Basics | Intro to VHDL | Counter (VHDL)
Week 6: Midterm 1 (Friday, 10/4/2019); | Intro to VHDL (Part 2) | LFSR | Gray Counter | Register File | FIFO
Conditional Assignment | Hamming Code | ASM Charts | ASM Charts Diagrams | ( 2 ) | FSM-VHDL
Parity (Verilog) | Parity (VHDL) | CRC | Display |
Week 9: SRAM Handout, | (2) | (3) | mem_fsm | mem_top
Week 10: Metastability, | (1) | (2) | Midterm 2 Review
******************************************************************************************************** * Week 10: Midterm 2 Review. Week 11: Miderm 2 * Week 10: Oct. 28 ~ Nov. 1; Week 11: Nov. 4 ~ Nov. 8 ********************************************************************************************************
Week 11: Hazards, | Extra | Midterm 2
Week 12: VGA | ( 1 ) | ( 2 ) | ( 3 )
Week 13: CPLD & FPGA Architecture
Week 14: JTAG Boundary Scan (P1) | ( P2 ) | EXTEST
Week 15: Transmission Line | Clock Termination Techniques
