Introduction | Ex_S0 | | Gate Level in Verilog | Testbench in Verilog
Hiearchical Design @ Gate Level (c4) | Gate Level in Verilog (c5) | Ex_S1 | Carry Select Adder | Gate Level in Verilog (c6)
********************************************** * FPGA Pins * **********************************************
Behavioral Design (c7) | Ex_S2 | Queues, FSM (c12) | Mult | Ex_S3
Multiplexed Character Display | FPGA Fun (Pins) | Verilog Assignments with Delays (c7) | Verilog Behavioral Modelling (c8)
******************************************************************************************************** * Week 5: Midterm 1 Review. Week 6: Miderm 1 * Week 5: Sep. 23~27; Week 6: Sep. 30 ~ Oct. 4 ********************************************************************************************************
VHDL Basics | VHDL Introduction | Xilinx ILA | Display Counter
Sequential Circuit Design in VHDL | Ex_S4
******************************************************************************************************** ASM Charts | Ex_S5 | Ex_S6 | Concurrent Signals | Ex_S7
Error Detection & Correction | Hamming Code | Comb. Practice in VHDL