Course Annoucements:
1. Because 9/2/2019 (Monday) is holiday, Lab2 part 1 demo for Monday lab students will be extended to Week 5 Monday lab session.
All other labs of lab 2 will still follow the schedule posted on the syllabus.
Lab2 Report schedule will also follow the schedule posted on the syllabus.
2. Quiz 1: Friday 9/13/2019 inside classroom.
Quiz 1: close book, close notes and no cheat-sheets.
Quiz 1: you need to review half adder design and testbench, mux2to1 design and testbench,
any general combinational circuit design when schemtic is given and testbench,
basic rising edge triggered D Flip-flop design and testbench before you attend the quiz.
All of students must take the quiz1 on Friday 9/13/2019.
No make-up quiz will be given if you miss the quiz.
Your quiz 1 grade will be zero if you miss the quiz inside your classroom on Friday of 9/13/2019.
3. *** Important Announcement ****
Week 6: Midterm 1 (Friday, 10/4/2019)
Introduction | Ex_S0 (basic) | Gate Level in Verilog | Testbench in Verilog
Ex_S1 (adders) | Full Adder | Ex_S1.1(different mux) | Ex_RCA4(4-bit Ripple Carry Adder) | Carry Select Adder | Hiearchical Design(Gate Level)
Ex_S2 (D Flip-Flops, Shift Registers, Adder) | Mult | Ex_S3 (FSM) | Queues, FSM | Behavioral Design (c7)
********************************************** * FPGA Pins * **********************************************
Multiplexed Character Display | FPGA Fun (Pins) | Behavioral Design (c7) | Verilog Behavioral Modelling (c8)
******************************************************************************************************** * Week 5: Midterm 1 Review. Week 6: Miderm 1 * Week 5: Sep. 23~27; Week 6: Sep. 30 ~ Oct. 4 ********************************************************************************************************
Week 5: Midterm Review; | VHDL Basics | Intro to VHDL | Counter (VHDL)
Week 6: Midterm 1 (Friday, 10/4/2019); | Intro to VHDL (Part 2) | LFSR | Gray Counter | Register File