Introduction | c1: Architectural Perspective |
c2: Architecture Overview | demo.v & demo_tb.v, | displayed results, | reading | More: cir.v & cir_tb.v | myand.v & cir_tb.v | displayed results (2)
c4: Packet Based Transactions (P1) | c4: Packet Based Transactions (P2) | 32-bit LCRC | General CRC | ( 2 ) | ( 3 ) | CRC for DLLP |
c5: ACK/NAK Protocol (P1) | (P2) | (P3) | fifo diagram | fifo | ram | (2) | tb_mydesign_ram | result
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Week 5: Feb. 17 ~ Feb.21
Week 5: Midterm 1 Review
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c3: Address Spaces & Transaction Routing |
c6: QoS/TCs/VCs and Arbitration | midterm 1
c7: Flow Control | Dice | Max_Payload_Size |
c8: Transaction Ordering | ( RO ) | c8: Transaction Ordering (Part 2) |
c10: Error Detection & Handling (Part 1) | (Part 2) | (Part 3) |
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Week 10: Mar. 23 ~ Mar.27
Week 10: Midterm 2 Review
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c9: Interrupts |
Handout: EMC, Cabling, Shielding, Grounding, Digital Circuit Noise and Layout |
