Week 1: Introduction | Gate Level Design | Set 1 | Set 2 | Set 3
Week 2: Gate Level - 2 | Behavioral | Beh-2 | Set 4 | Set 5 | Set 6 | Set 7
Week 3: Queues, FSM | Multiplexed Display | Set 8 | Set 9 | Set 10
Week 4: Functions & Tasks
| System Functions and Tasks
| Set 11
| Set 12
| Set 13
Midterm 1 Review
Week 5: Midterm 1 Review;
| VHDL Constructs
| VHDL Concurrency
| Set 14
| Set 15
********************************************************************************************************
********* Week 6: Miderm 1 ***********
********************************************************************************************************
Week 6: Midterm 1 (Wednesday); | Counter (VHDL) | VHDL Constructs | LFSR
Weeks 7 & 8: Conditional Assignment
| Hamming Code
| ASM Charts
| ASM Charts Diagrams
| ( 2 )
| FSM-VHDL
Exercise: FSM,
| ( 1 )
| ( 2 )
| ( 3 )
| ( cir )
| ( cir2 )
| ( cir3 )
Exercise: Gray Counter
| ASM Chart
| ( cir4 )
| DICE
Parity (Verilog) | Parity (VHDL) | CRC | Display |
Week 9: SRAM Handout (1), | decoder | SRAM (2) | SRAM (3) | mem_fsm | mem_top | FIFO
Week 10: Metastability, | (1) | (2) | Midterm 2 Review
******************************************************************************************************** * Week 10: Midterm 2 Review. Week 11: Miderm 2 * Week 10: Mar. 23 ~ Mar. 27; Week 11: Apr. 6 ~ Apr. 10 ********************************************************************************************************
Week 11: Hazards, | Extra | Exe2 | Exe3 | Midterm 2
Week 12: VGA | ( 1 ) | ( 2 ) | ( 3 ) | ( 4 )
Week 13: CPLD & FPGA Architecture | ILA
Week 14: JTAG Boundary Scan (P1) | ( P2 ) | EXTEST
Week 15: Transmission Line | (2) | Clock Termination Techniques
