Week 1: Introduction | Gate Level Design | ( W1 - Set )
Week 2: Gate Level - 2 | Behavioral | Behavioral-2
Week 3: Queues, FSM | ( W3 - Set.1 ) | ( W3 - Set.2 ) | ( W3 - Set.3 )
Week 4: Functions & Tasks | System Functions and Tasks
Week 5: VHDL Constructs | VHDL Concurrency | Synthesis
Week 6: Error Dection & Correctioon | LFSR, CRC
Week 7: Resource Sharing, & Other general circuits,
| LFSR, CRC
| Midterm Review
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********* Week 7: Miderm Review ***********
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Week 8: Sequencial, Variable, Register File
| Poor Design, Timer, Pulse, & FIFO
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********* Week 9: Miderm ***********
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Week 9:Metastability | Midterm; | CAM, Pipeline
Week 10: ASM Charts | ASMD | ASMD (2)
Week 11: SRAM Handout (1), | decoder | SRAM (2) | SRAM (3) | mem_fsm | mem_top
Week 12: VGA | ( 1 ) | ( 2 ) | ( 3 ) | ( 4 )
Week 13: CPLD & FPGA Architecture | ILA
Week 14: JTAG Boundary Scan (P1) | ( P2 ) | EXTEST
Week 15: Transmission Line | (2) | Clock Termination Techniques
Week 6: Midterm 1 (Wednesday); | Counter (VHDL) | VHDL Constructs | LFSR
Weeks 7 & 8: Conditional Assignment
| Hamming Code
| ASM Charts
| ASM Charts Diagrams
| ( 2 )
| FSM-VHDL
Exercise: FSM,
| ( 1 )
| ( 2 )
| ( 3 )
| ( cir )
| ( cir2 )
| ( cir3 )
Exercise: Gray Counter
| ASM Chart
| ( cir4 )
| DICE
Parity (Verilog) | Parity (VHDL) | CRC | Display |
Week 9: SRAM Handout (1), | decoder | SRAM (2) | SRAM (3) | mem_fsm | mem_top | FIFO
Week 10: Metastability, | (1) | (2) | Midterm 2 Review
******************************************************************************************************** * Week 10: Midterm 2 Review. Week 11: Miderm 2 * Week 10: Mar. 23 ~ Mar. 27; Week 11: Apr. 6 ~ Apr. 10 ********************************************************************************************************
Week 11: Hazards, | Extra | Exe2 | Exe3 | Midterm 2
